Projects

project_and_non_project_mode

VHDL

No description.

Image-Accellerator

SystemVerilog

This project involve the CNN but it is done through designing the chip which will handle everything during the time of the image capturing

FPGA_master_class_lab1

Verilog

In this lab we are implementing the ALU for OR,AND,XOR,and XNOR. Then the result of the ALU is displayed on the 7segment display board of the Urbana board

Mini-Lab-Project-on-Verilog

Verilog

This project is all about creating, a generator which generate the power of 3 numbers and send through FIFO to the Memory Controller then Memory. We have used the AXI-STREAM interface

fir_filter

C++

This project implements a Finite Impulse Response (FIR) filter using SystemC. The FIR filter processes input signals and produces output signals based on predefined coefficients. The design includes a testbench to validate the functionality of the FIR filter.

my_research_tool

Python

This research tool is built using Python. The aim of this app to streamline the work of categorising the research paper.

MBED_smart_traffic_ads

Other

No description.

Pangaea

SCSS

This is an official website for Pangaea Tech

TBClassification

Other

No description.